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LT3575 1 3575f features applications description isolated flyback converter without an opto-coupler the lt ? 3575 is a monolithic switching regulator speci? c- ally designed for the isolated ? yback topology. no third winding or optoisolator is required for regulation. the part senses the isolated output voltage directly from the primary side ? yback waveform. a 2.5a, 60v npn power switch is integrated along with all control logic into a 16-lead tssop package. the LT3575 operates with input supply voltages from 3v to 40v, and can deliver output power up to 14w with no external power switch.the LT3575 utilizes boundary mode operation to provide a small magnetic solution with improved load regulation. the output voltage is easily set with two external resistors and the transformer turns ratio. off the shelf transformers are available for many applications. 5v isolated flyback converter n 3v to 40v input voltage range n 2.5a, 60v integrated npn power switch n boundary mode operation n no transformer third winding or optoisolator required for regulation n improved primary-side winding feedback load regulation n v out set with two external resistors n bias pin for internal bias supply and power npn driver n programmable soft-start n programmable power switch current limit n thermally enhanced 16-lead tssop n industrial, automotive and medical isolated power supplies load regulation shdn /uvlo tc r ilim ss r fb r ref sw vc gnd test bias LT3575 3575 ta01 28.7k 10k 11.5k v in 12v to 24v v in 357k 51.1k 10 f 0.22 f1k 24 h 10nf 4.7nf 4.7 f 6.04k 80.6k v out + 5v, 1.4a v out C 3:1 2.6 h47 f i out (a) 0 output voltage error (%) 0 C1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 C2 1 3575 ta01b v in = 12v v in = 24v typical application l , lt, ltc, ltm, burst mode, linear technology and the linear logo are registered trademarks and no rsense and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. datasheet.in
LT3575 2 3575f absolute maximum ratings sw ............................................................................60v v in , shdn /uvlo, r fb , bias .....................................40v ss, v c , tc, r ref , r ilim ..............................................5v maximum junction temperature .......................... 125c operating junction temperature range (note 2) LT3575e, LT3575i .............................. C40c to 125c storage temperature range .................. C65c to 150c order information electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 12v, unless otherwise noted. lead free finish tape and reel part marking* package description temperature range LT3575efe#pbf LT3575efe#trpbf 3575fe 16-lead plastic tssop C40c to 125c LT3575ife#pbf LT3575ife#trpbf 3575fe 16-lead plastic tssop C40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ parameter conditions min typ max units input voltage range l 340v quiescent current ss = 0v v shdn /uvlo = 0v 4.5 01 ma a soft-start current ss = 0.4v 7 a shdn /uvlo pin threshold uvlo pin voltage rising l 1.15 1.22 1.32 v shdn /uvlo pin hysteresis current v uvlo = 1v 2.2 2.8 3.2 a soft-start threshold 0.7 v maximum switching frequency 1000 khz switch current limit r ilim = 10k 2.8 3.5 4.2 a minimum current limit v c = 0v 400 ma switch v cesat i sw = 0.5a 75 125 mv r ref voltage v in = 3v l 1.21 1.20 1.23 1.25 1.26 v r ref voltage line regulation 3v < v in < 40v 0.01 0.03 %/ v r ref pin bias current (note 3) l 100 600 na pin configuration fe package 16-lead plastic tssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 nc nc gnd test tc r ref r fb v c nc v in sw sw bias shdn /uvlo ss r ilim 17 gnd t jmax = 125c, ja = 38c/w, jc = 10c/w exposed pad (pin 17) is gnd, must be connected to gnd datasheet.in
LT3575 3 3575f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LT3575e is guaranteed to meet performance speci? cations from 0c to 125c junction temperature. speci? cations over the C40c to 125c operating junction temperature range are assured by design characterization and correlation with statistical process controls. the LT3575i is guaranteed over the full C40c to 125c operating junction temperature range. note 3: current ? ows out of the r ref pin. parameter conditions min typ max units i ref reference current measured at r fb pin with r ref = 6.49k 190 a error ampli? er voltage gain v in = 3v 150 v/v error ampli? er transconductance i = 10a, v in = 3v 150 mhos minimum switching frequency v c = 0.35v 40 khz tc current into r ref r tc = 20.1k 27.5 a bias pin voltage i bias = 30ma 2.9 3 3.1 v electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 12v, unless otherwise noted. typical performance characteristics output voltage quiescent current bias pin voltage t a = 25c, unless otherwise noted. temperature (c) C50 4.80 v out (v) 4.85 4.95 5.00 5.05 5.20 5.15 0 50 75 4.90 5.10 C25 25 100 125 3575 g01 temperature (c) C50 0 i q (ma) 2 3 4 8 6 7 0 50 75 1 5 C25 25 100 125 3575 g02 v in = 40v with bias = 20v v in = 5v with bias = 5v temperature (c) C50 2.0 bias voltage (v) 2.4 2.6 2.8 3.2 0 50 75 2.2 3.0 C25 25 100 125 3575 g03 v in = 40v v in = 12v datasheet.in
LT3575 4 3575f typical performance characteristics switch saturation voltage switch current limit switch current limit vs r ilim shdn /uvlo falling threshold ss pin current t a = 25c, unless otherwise noted. switch current (ma) 0 0 switch v cesat voltage (mv) 100 200 250 400 350 500 1000 2000 1500 2500 500 50 150 300 450 3000 3575 g04 125 c 25 c C50 c temperature (c) C50 current limit (a) 2.5 3 3.5 4 2.0 C25 25 0 50 75 100 125 0.5 0 1.5 4.5 1 3575 g05 max i lim min i lim temperature (c) C50 shdn /uvlo voltage (v) 1.24 1.26 1.22 25 C25 050 100 75 125 1.20 1.18 1.28 3575 g07 r ilim resistance (k) 0 switch current limit (a) 3 3.5 2.5 2 10 30 20 40 50 60 0.5 0 1.5 4 1 3575 g06 temperature (c) C60 ss pin current (a) 8 10 80 6 4 C20 20 C40 120 040 100 60 140 2 0 12 3575 g08 datasheet.in
LT3575 5 3575f pin functions nc (pins 1, 15, 16) : no connect pins. can be left open or connected to any ground plane. v in (pin 2) : input voltage. this pin supplies current to the internal start-up circuitry and as a reference voltage for the dcm comparator and feedback circuitry. this pin must be locally bypassed with a capacitor. sw (pins 3, 4) : collector node of the output switch. this pin has large currents ? owing through it. keep the traces to the switching components as short as possible to minimize electromagnetic radiation and voltage spikes. bias (pin 5) : bias voltage. this pin supplies current to the switch driver and internal circuitry of the LT3575. this pin must be locally bypassed with a capacitor. this pin may also be connected to v in if a third winding is not used and if v in 15v. if a third winding is used, the bias voltage should be lower than the input voltage for proper operation. shdn /uvlo (pin 6) : shutdown/undervoltage lockout. a resistor divider connected to v in is tied to this pin to program the minimum input voltage at which the LT3575 will operate. at a voltage below ~0.7v, the part draws no quiescent current. when below 1.22v and above ~0.7v, the part will draw 7a of current, but internal circuitry will remain off. above 1.22v, the internal circuitry will start and a 7a current will be fed into the ss pin. when this pin falls below 1.22v, 2.8a will be pulled from the pin to provide programmable hysteresis for uvlo. ss (pin 7) : soft-start pin. place a soft-start capacitor here to limit start-up inrush current and output voltage ramp rate. switching starts when the voltage at this pin reaches ~0.7v. r ilim (pin 8) : maximum current limit adjust pin. a resistor should be tied to this pin to ground to set the current limit. use a 10k resistor for the full current capabilities of the switch. v c (pin 9) : compensation pin for internal error ampli? er. connect a series rc from this pin to ground to compensate the switching regulator. a 100pf capacitor in parallel helps eliminate noise. r fb (pin 10) : input pin for external feedback resistor. this pin is connected to the transformer primary (v sw ). the ratio of this resistor to the r ref resistor, times the internal bandgap reference, determines the output voltage (plus the effect of any non-unity transformer turns ratio). the average current through this resistor during the ? yback period should be approximately 200a. for nonisolated applications, this pin should be connected to v in . r ref (pin 11) : input pin for external ground-referred reference resistor. this resistor should be in the range of 6k, but for convenience, need not be precisely this value. for nonisolated applications, a traditional resistor voltage divider may be connected to this pin. tc (pin 12) : output voltage temperature compensation. connect a resistor to ground to produce a current proportional to absolute temperature to be sourced into the r ref node. i tc = 0.55v/r tc . test (pin 13): this pin is used for testing purposes only and must be connected to ground for the part to operate properly. gnd (pin 14, exposed pad pin 17): ground. the exposed pad of the package provides both electrical contact to ground and good thermal contact to the printed circuit board. the exposed pad must be soldered to the circuit board for proper operation and should be well connected with many vias to an internal ground plane. datasheet.in
LT3575 6 3575f block diagram flyback error amp master latch current comparator bias r1 r2 c3 r6 v out + v out C v in tc bias ss sw v in v in gnd v1 120mv 1.23v v c d1 t1 n:1 i1 7a i2 20a r sense 0.01 c2 c1 l1a l1b r3 r4 c5 + C internal reference and regulators oscillator tc current one shot r q s s g m + C a1 + C a5 + C + C a2 a4 2.8a + C 3573 bd q2 r7 c4 r5 q3 1.22v q4 q1 driver shdn /uvlo r ilim r fb r ref datasheet.in
LT3575 7 3575f operation the LT3575 is a current mode switching regulator ic designed speci? cally for the isolated ? yback topology. the special problem normally encountered in such circuits is that information relating to the output voltage on the isolated secondary side of the transformer must be communicated to the primary side in order to maintain regulation. historically, this has been done with optoisolators or extra transformer windings. optoisolator circuits waste output power and the extra components increase the cost and physical size of the power supply. optoisolators can also exhibit trouble due to limited dynamic response, nonlinearity, unit-to-unit variation and aging over life. circuits employing extra transformer windings also exhibit de? ciencies. using an extra winding adds to the transformers physical size and cost, and dynamic response is often mediocre. the LT3575 derives its information about the isolated output voltage by examining the primary side ? yback pulse waveform. in this manner, no optoisolator nor extra transformer winding is required for regulation. the output voltage is easily programmed with two resistors. since this ic operates in boundary control mode, the output voltage is calculated from the switch pin when the secondary current is almost zero. this method improves load regulation without external resistors and capacitors. the block diagram shows an overall view of the system. many of the blocks are similar to those found in traditional switching regulators including: internal bias regulator, oscillator, logic, current ampli? er and comparator, driver, and output switch. the novel sections include a special ? yback error ampli? er and a temperature compensation circuit. in addition, the logic system contains additional logic for boundary mode operation, and the sampling error ampli? er. the LT3575 features a boundary mode control method, where the part operates at the boundary between continuous conduction mode and discontinuous conduction mode. the v c pin controls the current level just as it does in normal current mode operation, but instead of turning the switch on at the start of the oscillator period, the part detects when the secondary side winding current is zero. boundary mode operation boundary mode is a variable frequency, current-mode switching scheme. the switch turns on and the inductor current increases until a v c pin controlled current limit. the voltage on the sw pin rises to the output voltage divided by the secondary-to-primary transformer turns ratio plus the input voltage. when the secondary current through the diode falls to zero, the sw pin voltage falls below v in . a discontinuous conduction mode (dcm) comparator detects this event and turns the switch back on. boundary mode returns the secondary current to zero every cycle, so the parasitic resistive voltage drops do not cause load regulation errors. boundary mode also allows the use of a smaller transformer compared to continuous conduction mode and no subharmonic oscillation. at low output currents the LT3575 delays turning on the switch, and thus operates in discontinuous mode. unlike a traditional ? yback converter, the switch has to turn on to update the output voltage information. below 0.6v on the v c pin, the current comparator level decreases to its minimum value, and the internal oscillator frequency decreases in frequency. with the decrease of the internal oscillator, the part starts to operate in dcm. the output current is able to decrease while still allowing a minimum switch off-time for the error amp sampling circuitry. the typical minimum internal oscillator frequency with v c equal to 0v is 40khz. datasheet.in
LT3575 8 3575f error amplifierpseudo dc theory in the block diagram, the r ref (r4) and r fb (r3) resistors can be found. they are external resistors used to program the output voltage. the LT3575 operates much the same way as traditional current mode switchers, the major difference being a different type of error ampli? er which derives its feedback information from the ? yback pulse. operation is as follows: when the output switch, q1, turns off, its collector voltage rises above the v in rail. the amplitude of this ? yback pulse, i.e., the difference between it and v in , is given as: v flbk = (v out + v f + i sec ? esr) ? n ps v f = d1 forward voltage i sec = transformer secondary current esr = total impedance of secondary circuit n ps = transformer effective primary-to-secondary turns ratio the ? yback voltage is then converted to a current by the action of r fb and q2. nearly all of this current ? ows through resistor r ref to form a ground-referred voltage. this voltage is fed into the ? yback error ampli? er. the ? yback error ampli? er samples this output voltage information when the secondary side winding current is zero. the error ampli? er uses a bandgap voltage, 1.23v, as the reference voltage. the relatively high gain in the overall loop will then cause the voltage at the r ref resistor to be nearly equal to the bandgap reference voltage v bg . the relationship between v flbk and v bg may then be expressed as: v r v r or vv r r flbk fb bg ref flbk bg fb ref ? ? ? ? ? ? = = ? , ? ? ? ? ? ? ? ? ? ? ? ? 1 = ratio of q1 i c to i e , typically 0.986 v bg = internal bandgap reference in combination with the previous v flbk expression yields an expression for v out , in terms of the internal reference, programming resistors, transformer turns ratio and diode forward voltage drop: vv r rn vi es out bg fb ref ps fsec = ? ? ? ? ? ? ? ? ? ? ? ? ?? 1 (r r) additionally, it includes the effect of nonzero secondary output impedance (esr). this term can be assumed to be zero in boundary control mode. more details will be discussed in the next section. temperature compensation the ? rst term in the v out equation does not have a tem- perature dependence, but the diode forward drop has a signi? cant negative temperature coef? cient. to compen- sate for this, a positive temperature coef? cient current source is connected to the r ref pin. the current is set by a resistor to ground connected to the tc pin. to cancel the temperature coef? cient, the following equation is used: v t r rn v t or r r nv ffb tc ps tc tc fb ps =? = ? ?? , ? 1 1 f f tc fb ps t v t r n / ? ( v f / t ) = diodes forward voltage temperature coef? cient ( v tc / t) = 2mv v tc = 0.55v the resistor value given by this equation should also be veri? ed experimentally, and adjusted if necessary to achieve optimal regulation overtemperature. the revised output voltage is as follows: vv r rn v v r out bg fb ref ps f tc tc = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 ? ? ? ? ? ? ??() r n iesr fb ps sec applications information datasheet.in
LT3575 9 3575f applications information error amplifierdynamic theory due to the sampling nature of the feedback loop, there are several timing signals and other constraints that are required for proper LT3575 operation. minimum current limit the LT3575 obtains output voltage information from the sw pin when the secondary winding conducts current. the sampling circuitry needs a minimum amount of time to sample the output voltage. to guarantee enough time, a minimum inductance value must be maintained. the primary side magnetizing inductance must be chosen above the following value: lv t i nv n h v pri out min min ps out ps = ? ? ? ? ?? ?? . 088 ? ? ? t min = minimum off-time, 350ns i min = minimum current limit, 400ma the minimum current limit is higher than that on the elec- trical characteristics table due to the overshoot caused by the comparator delay. leakage inductance blanking when the output switch ? rst turns off, the ? yback pulse appears. however, it takes a ? nite time until the transformer primary side voltage waveform approximately represents the output voltage. this is partly due to the rise time on the sw node, but more importantly due to the trans- former leakage inductance. the latter causes a very fast voltage spike on the primary side of the transformer that is not directly related to output voltage (some time is also required for internal settling of the feedback ampli? er circuitry). the leakage inductance spike is largest when the power switch current is highest. in order to maintain immunity to these phenomena, a ? xed delay is introduced between the switch turn-off command and the beginning of the sampling. the blanking is internally set to 150ns. in certain cases, the leakage inductance may not be settled by the end of the blanking period, but will not signi? cantly affect output regulation. selecting r fb and r ref resistor values the expression for v out, developed in the operation section, can be rearranged to yield the following expression for r fb : r rnv v v v fb ref ps out f tc bg = + () + ? ? ? ? ? where, v out = output voltage v f = switching diode forward voltage = ratio of q1, ic to ie, typically 0.986 n ps = effective primary-to-secondary turns ratio v tc = 0.55v the equation assumes the temperature coef? cients of the diode and v tc are equal, which is a good ? rst-order approximation. strictly speaking, the above equation de? nes r fb not as an absolute value, but as a ratio of r ref . so, the next question is, what is the proper value for r ref ? the answer is that r ref should be approximately 6.04k. the LT3575 is trimmed and speci? ed using this value of r ref . if the impedance of r ref varies considerably from 6.04k, additional errors will result. however, a variation in r ref of several percent is acceptable. this yields a bit of freedom in selecting standard 1% resistor values to yield nominal r fb /r ref ratios. the r fb resistor given by this equation should also be veri? ed experimentally, and adjusted if necessary for best output accuracy. tables 1-4 are useful for selecting the resistor values for r ref and r fb with no equations. the tables provide r fb , r ref and r tc values for common output voltages and common winding ratios. table 1. common resistor values for 1:1 transformers v out (v) n ps r fb (k) r ref (k) r tc (k) 3.3 1.00 18.7 6.04 19.1 5 1.00 27.4 6.04 28 12 1.00 64.9 6.04 66.5 15 1.00 80.6 6.04 80.6 20 1.00 107 6.04 105 datasheet.in
LT3575 10 3575f applications information table 2. common resistor values for 2:1 transformers v out (v) n ps r fb (k) r ref (k) r tc (k) 3.3 2.00 37.4 6.04 18.7 5 2.00 56 6.04 28 12 2.00 130 6.04 66.5 15 2.00 162 6.04 80.6 table 3. common resistor values for 3:1 transformers v out (v) n ps r fb (k) r ref (k) r tc (k) 3.3 3.00 56.2 6.04 20 5 3.00 80.6 6.04 28.7 10 3.00 165 6.04 54.9 table 4. common resistor values for 4:1 transformers v out (v) n ps r fb (k) r ref (k) r tc (k) 3.3 4.00 76.8 6.04 19.1 5 4.00 113 6.04 28 output power a ? yback converter has a complicated relationship between the input and output current compared to a buck or a boost. a boost has a relatively constant maximum input current regardless of input voltage and a buck has a relatively constant maximum output current regardless of input voltage. this is due to the continuous nonswitching behavior of the two currents. a ? yback converter has both discontinuous input and output currents which makes it similar to a nonisolated buck-boost. the duty cycle will affect the input and output currents, making it hard to predict output power. in addition, the winding ratio can be changed to multiply the output current at the expense of a higher switch voltage. the graphs in figures 1-3 show the maximum output power possible for the output voltages 3.3v, 5v, and 12v. the maximum power output curve is the calculated output power if the switch voltage is 50v during the off-time. to achieve this power level at a given input, a winding ratio value must be calculated to stress the switch to 50v, resulting in some odd ratio values. the curves below are examples of common winding ratio values and the amount of output power at given input voltages. one design example would be a 5v output converter with a minimum input voltage of 20v and a maximum input voltage of 30v. a three-to-one winding ratio ? ts this design example perfectly and outputs close to ten watts at 30v but lowers to eight watts at 20v. transformer design considerations transformer speci? cation and design is perhaps the most critical part of successfully applying the LT3575. in addition to the usual list of caveats dealing with high frequency isolated power supply transformer design, the following information should be carefully considered. linear technology has worked with several leading magnetic component manufacturers to produce pre-designed ? yback transformers for use with the LT3575. table 5 shows the details of several of these transformers. figure 1. output power for 3.3v output figure 2. output power for 5v output figure 3. output power for 12v output input voltage (v) 0 output power (w) 10 12 35 8 6 10 20 5 15 25 40 30 45 0 4 14 2 3573 f02 5:1 4:1 maximum output power 7:1 1:1 2:1 3:1 max p out input voltage (v) 0 output power (w) 10 12 35 8 6 10 20 5 15 25 30 40 0 4 14 2 3573 f03 maximum output power 1:1 2:1 3:1 max p out 7:1 5:1 input voltage (v) 0 output power (w) 10 12 40 8 6 10 20 5 15 25 35 30 45 2 0 4 14 3575 f01 maximum output power 10:1 1:1 2:1 3:1 4:1 max p out datasheet.in
LT3575 11 3575f applications information table 5. predesigned transformerstypical speci? cations, unless otherwise noted transformer part number dimension (w l h) (mm) l pri (h) l leakage (nh) n p :n s r pri (m) r sec (m) vendor target application* v o (v) i o (a) 750311306 15.24 13.3 11.43 100 1750 3:1 285 46 wrth elektronik 12 1 750311307 15.24 13.3 11.43 100 2000 2:1 290 104 wrth elektronik 24 0.5 750311308 15.24 13.3 11.43 100 2100 1:1 325 480 wrth elektronik 24 0.5 750310564 15.24 13.3 11.43 63 450 3:1 115 50 wrth elektronik 5 1 750311303 15.24 13.3 11.43 50 800 5:1 106 13 wrth elektronik 5 3 750311304 15.24 13.3 11.43 50 800 4:1 146 17 wrth elektronik 5 3 750311305 15.24 13.3 11.43 50 1200 3:1 175 28 wrth elektronik 12 1 pa2627nl 15.24 13.3 11.43 50 766 3:1 420 44 pulse engineering 3.3 3 750310471 15.24 13.3 11.43 25 350 3:1 57 11 wrth elektronik 5 2 750310562 15.24 13.3 11.43 25 330 2:1 60 20 wrth elektronik 12 0.8 750310563 15.24 13.3 11.43 25 325 1:1 60 60 wrth elektronik 12 0.8 pa2364nl 15.24 13.3 11.43 25 1000 7:1 125 5.6 pulse engineering 3.3 1.5 pa2363nl 15.24 13.3 11.43 25 850 5:1 117 7.5 pulse engineering 5 1 pa2362nl 15.24 13.3 11.43 24 550 4:1 117 9.5 pulse engineering 3.3 1.5 pa2454nl 15.24 13.3 11.43 24 430 3:1 82 11 pulse engineering 5 1 pa2455nl 15.24 13.3 11.43 25 450 2:1 82 22 pulse engineering 12 0.5 pa2456nl 15.24 13.3 11.43 25 390 1:1 82 84 pulse engineering 12 0.3 750310559 15.24 13.3 11.43 24 400 4:1 51 16 wrth elektronik 3.3 1.5 750311675 15.24 13.3 11.43 25 130 3:1 51 11 wrth elektronik 5 2 750311342 15.24 13.3 11.43 15 440 2:1 85 22 wrth elektronik 5 1.5 750311567 15.24 13.3 11.43 8 425 2:1 53 22 wrth elektronik 5 2 750311422 17.7 14.0 12.7 50 574 5:1 80 8 wrth elektronik 3.3 4 750311423 17.7 14.0 12.7 50 570 4:1 90 12 wrth elektronik 5 2.4 750311457 17.7 14.0 12.7 50 600 4:1 115 12 wrth elektronik 5 2.4 750311688 17.7 14.0 12.7 50 600 5:1 80 8 wrth elektronik 3.3 4 750311689 17.7 14.0 12.7 50 600 4:1 115 12 wrth elektronik 5 2.4 750311439 17.7 14.0 12.7 37 750 2:1 89 28 wrth elektronik 12 1 pa2467nl 17.7 14.0 12.7 37 750 2:1 89 28 pulse engineering 12 1 pa2466nl 17.7 14.0 12.7 37 750 6:1 89 4.6 pulse engineering 3.3 4 pa2369nl 17.7 14.0 12.7 37 750 5:1 89 6.2 pulse engineering 5 2.5 750311458 17.7 14.0 12.7 15 175 3:1 35 6 wrth elektronik 3.3 4 750311625 17.7 14.0 12.7 9 350 4:1 43 6 wrth elektronik 3.3 4 750311564 17.7 14.0 12.7 9 120 3:1 36 7 wrth elektronik 5 2.5 750311624 17.7 14.0 12.7 9 180 3:2 34 21 wrth elektronik 15 1 *target applications, not guaranteed datasheet.in
LT3575 12 3575f applications information turns ratio note that when using an r fb /r ref resistor ratio to set output voltage, the user has relative freedom in selecting a transformer turns ratio to suit a given application.in contrast, simpler ratios of small integers, e.g., 1:1, 2:1, 3:2, etc., can be employed to provide more freedom in setting total turns and mutual inductance. typically, the transformer turns ratio is chosen to maximize available output power. for low output voltages (3.3v or 5v), a n:1 turns ratio can be used with multiple primary windings relative to the secondary to maximize the transformers current gain (and output power). however, remember that the sw pin sees a voltage that is equal to the maximum input supply voltage plus the output voltage multiplied by the turns ratio. this quantity needs to remain below the abs max rating of the sw pin to prevent breakdown of the internal power switch. together these conditions place an upper limit on the turns ratio, n, for a given application. choose a turns ratio low enough to ensure: n vv vv in max out f < + 50 ? () for larger n:1 values, a transformer with a larger physical size is needed to deliver additional current and provide a large enough inductance value to ensure that the off-time is long enough to accurately measure the output voltage. for lower output power levels, a 1:1 or 1:n transformer can be chosen for the absolute smallest transformer size. a 1: n transformer will minimize the magnetizing inductance (and minimize size), but will also limit the available output power. a higher 1:n turns ratio makes it possible to have very high output voltages without exceeding the breakdown voltage of the internal power switch. leakage inductance transformer leakage inductance (on either the primary or secondary) causes a voltage spike to appear at the primary after the output switch turns off. this spike is increasingly prominent at higher load currents where more stored energy must be dissipated. in most cases, a snubber circuit will be required to avoid overvoltage breakdown at the output switch node. transformer leakage inductance should be minimized. an rcd (resistor capacitor diode) clamp, shown in figure 4, is required for most designs to prevent the leakage inductance spike from exceeding the breakdown voltage of the power device. the ? yback waveform is depicted in figure 5. in most applications, there will be a very fast voltage spike caused by a slow clamp diode that may not exceed 60v. once the diode clamps, the leakage inductance current is absorbed by the clamp capacitor. this period should not last longer than 150ns so as not to interfere with the output regulation, and the voltage during this clamp period must not exceed 55v. the clamp diode turns off after the leakage inductance energy is absorbed and the switch voltage is then equal to: v sw(max) = v in(max) + n(v out + v f ) this voltage must not exceed 50v. this same equation also determines the maximum turns ratio. when choosing the snubber network diode, careful attention must be paid to maximum voltage seen by the sw pin. schottky diodes are typically the best choice to be used in the snubber, but some pn diodes can be used if they turn on fast enough to limit the leakage inductance spike. the leakage spike must always be kept below 60v. figures 6 and 7 show the sw pin waveform for a 24v in , 5v out application at a 1a load current. notice that the leakage spike is very high (more than 65v) with the bad diode, while the good diode effectively limits the spike to less than 55v. an alternative to rc network is a zener diode clamping. the zener diode must be able to handle the voltage rating and power dissipating during the switch turn-off time. application note 19 has more details on zener diode snubber design for ? yback converters. for applications with sw voltage exceeding 50v, zener diode clamp must be considered. at higher operating primary current, the leakage inductance spike can potentially exceed the breakdown voltage of the internal power switch. datasheet.in
LT3575 13 3575f figure 5. maximum voltages for sw pin flyback waveform figure 4. snubber clamping figure 6. good snubber diode limits sw pin voltage figure 7. bad snubber diode does not limit sw pin voltage < 50v < 55v < 60v v sw t off > 350ns time t sp < 150ns 3575 f05 100ns/div 10v/div 3575 f06 100ns/div 10v/div 3575 f07 3575 f04 l s d r clamp either zener or rc c applications information datasheet.in
LT3575 14 3575f secondary leakage inductance in addition to the previously described effects of leakage inductance in general, leakage inductance on the secondary in particular exhibits an additional phenomenon. it forms an inductive divider on the transformer secondary that effectively reduces the size of the primary-referred ? yback pulse used for feedback. this will increase the output voltage target by a similar percentage. note that unlike leakage spike behavior, this phenomenon is load independent. to the extent that the secondary leakage inductance is a constant percentage of mutual inductance (over manufacturing variations), this can be accommodated by adjusting the r fb /r ref resistor ratio. winding resistance effects resistance in either the primary or secondary will reduce overall efficiency (p out /p in ). good output voltage regulation will be maintained independent of winding resistance due to the boundary mode operation of the LT3575. bi? lar winding a bi? lar, or similar winding technique, is a good way to minimize troublesome leakage inductances. however, remember that this will also increase primary-to-secondary capacitance and limit the primary-to-secondary breakdown voltage, so, bi? lar winding is not always practical. the linear technology applications group is available and extremely quali? ed to assist in the selection and/or design of the transformer. setting the current limit resistor the maximum current limit can be set by placing a resistor between the r ilim pin and ground. this provides some ? exibility in picking standard off-the-shelf transformers that may be rated for less current than the LT3575s internal power switch current limit. if the maximum current limit is needed, use a 10k resistor. for lower current limits, the following equation sets the approximate current limit: raik ilim lim =?+ 65 10 3 5 10 3 ?(. ) the switch current limit vs r ilim plot in the typical performance characteristics section depicts a more accurate current limit. undervoltage lockout (uvlo) the shdn /uvlo pin is connected to a resistive voltage divider connected to v in as shown in figure 8. the voltage threshold on the shdn /uvlo pin for v in rising is 1.22v. to introduce hysteresis, the LT3575 draws 2.8a from the shdn /uvlo pin when the pin is below 1.22v. the hysteresis is therefore user-adjustable and depends on the value of r1. the uvlo threshold for v in rising is: v vr r r a r in uvlo rising (, ) .?( ) .? = + + 122 1 2 2 28 1 the uvlo threshold for v in falling is: v vr r r in uvlo falling (, ) .?( ) = + 122 1 2 2 to implement external run/stop control, connect a small nmos to the uvlo pin, as shown in figure 8. turning the nmos on grounds the uvlo pin and prevents the LT3575 from operating, and the part will draw less than a 1a of quiescent current. figure 8. undervoltage lockout (uvlo) LT3575 shdn /uvlo gnd r2 r1 v in 3575 f08 run/stop control (optional) applications information datasheet.in
LT3575 15 3575f applications information schematics in the typical applications section for other possible values). if too large of an r c value is used, the part will be more susceptible to high frequency noise and jitter. if too small of an r c value is used, the transient performance will suffer. the value choice for c c is somewhat the inverse of the r c choice: if too small a c c value is used, the loop may be unstable, and if too large a c c value is used, the transient performance will also suffer. transient response plays an important role for any dc/dc converter. design example the following example illustrates the converter design process using LT3575. given the input voltage of 20v to 28v, the required output is 5v, 1a. v in(min) = 20v, v in(max) = 28v, v out = 5v, v f = 0.5v and i out = 1a 1. select the transformer turns ratio to accommodate the output. the output voltage is re? ected to the primary side by a factor of turns ratio n. the switch voltage stress v sw is expressed as: n n n vvnvvv p s sw max in out f = =+ +< () ()50 or rearranged to: n v vv in max out f < ? + 50 () () on the other hand, the primary side current is multiplied by the same factor of n. the converter output capability is: idni d nv v vn out max pk out f in () .?( )? () =? = + + 08 1 1 2 ( () vv out f + minimum load requirement the LT3575 obtains output voltage information through the transformer while the secondary winding is conducting current. during this time, the output voltage (multiplied times the turns ratio) is presented to the primary side of the transformer. the LT3575 uses this re? ected signal to regulate the output voltage. this means that the LT3575 must turn on every so often to sample the output voltage, which delivers a small amount of energy to the output. this sampling places a minimum load requirement on the output of 1% to 2% of the maximum load. a zener diode with a zener breakdown of 20% higher than the output voltage can serve as a minimum load if pre-loading is not acceptable. for a 5v output, use a 6v zener with cathode connected to the output. bias pin considerations for applications with an input voltage less than 15v, the bias pin is typically connected directly to the v in pin. for input voltages greater than 15v, it is preferred to leave the bias pin separate from the v in pin. in this condition, the bias pin is regulated with an internal ldo to a voltage of 3v. by keeping the bias pin separate from the input voltage at high input voltages, the physical size of the capacitors can be minimized (the bias pin can then use a 6.3v or 10v rated capacitor). overdriving the bias pin with a third winding the LT3575 provides excellent output voltage regulation without the need for an optocoupler, or third winding, but for some applications with higher input voltages (>20v), it may be desirable to add an additional winding (often called a third winding) to improve the system ef? ciency. for proper operation of the LT3575, if a winding is used as a supply for the bias pin, ensure that the bias pin voltage is at least 3.15v and always less than the input voltage. for a typical 24v in application, overdriving the bias pin will improve the ef? ciency gain 4-5%. loop compensation the LT3575 is compensated using an external resistor- capacitor network on the v c pin. typical values are in the range of r c = 50k and c c = 1.5nf (see the numerous datasheet.in
LT3575 16 3575f applications information the transformer turns ratio is selected such that the converter has adequate current capability and a switch stress below 50v. table 6 shows the switch voltage stress and output current capability at different transformer turns ratio. table 6. switch voltage stress and output current capability vs turns-ratio n v sw(max) at v in(max) (v) i out(max) at v in(min) (a) duty cycle (%) 1:1 33.5 1.26 16~22 2:1 39 2.07 28~35 3:1 44.5 2.63 37~45 4:1 50 3.05 44~52 bias winding turns ratio is selected to program the bias voltage to 3v~5v. the bias voltage shall not exceed the input voltage. the turns ratio is then selected as primary: secondary: bias = 3:1:1. 2. select the transformer primary inductance for target switching frequency. the LT3575 requires a minimum amount of time to sample the output voltage during the off-time. this off-time, t off(min) , shall be greater than 350ns over all operating conditions. the converter also has a minimum current limit, i min , of 400ma to help create this off-time. this de? nes the minimum required inductance as de? ned as: l nv v i t min out f min off min = + () ? () the transformer primary inductance also affects the switching frequency which is related to the output ripple. if above the minimum inductance, the transformers primary inductance may be selected for a target switching frequency range in order to minimize the output ripple. the following equation estimates the switching frequency. f tt i v l i nv v l sw on off pk in pk ps out f = + = + + 11 () table 7.switching frequency at different primary inductance at i pk l (h) f sw at v in(min) (khz) f sw at v in(max) (khz) 15 174 205 30 87 103 60 44 51 note: the switching frequency is calculated at maximum output. in this design example, the minimum primary inductance is used to achieve a nominal switching frequency of 200khz at full load. the 750311458 from wrth elektronik is chosen as the ? yback transformer. given the turns ratio and primary inductance, a custom- ized transformer can be designed by magnetic component manufacturer or a multi-winding transformer such as a coiltronics versa-pac may be used. 3. select the output diodes and output capacitor. the output diode voltage stress v d is the summation of the output voltage and re? ection of input voltage to the secondary side. the average diode current is the load current. vv v n d out in =+ the output capacitor should be chosen to minimize the output voltage ripple while considering the increase in size and cost of a larger capacitor. the following equation calculates the output voltage ripple. v li cv max pk out = 2 2 4. select the snubber circuit to clamp the switch voltage spike. a ? yback converter generates a voltage spike during switch turn-off due to the leakage inductance of the transformer. in order to clamp the voltage spike below the maximum rating of the switch, a snubber circuit is used. there are many types of snubber circuits, for example r-c, r-c-d and datasheet.in
LT3575 17 3575f applications information zener clamps. among them, rcd is widely used. figure 9 shows the rcd snubber in a ? yback converter. a typical switch node waveform is shown in figure 10. during switch turn-off, the energy stored in the leakage inductance is transferred to the snubber capacitor, and eventually dissipated in the snubber resistor. 1 2 2 li f vv nv r spksw c c out = ? (?) the snubber resistor affects the spike amplitude v c and duration t sp , the snubber resistor is adjusted such that t sp is about 150ns. prolonged t sp may cause distortion to the output voltage sensing. the previous steps ? nish the ? yback power stage design. 5. select the feedback resistor for proper output voltage. using the resistor tables 1-4, select the feedback resistor r fb , and program the output voltage to 5v. adjust the r tc resistor for temperature compensation of the output voltage. r ref is selected as 6.04k. a small capacitor in parallel with r ref ? lters out the noise during the voltage spike, however, the capacitor should limit to 10pf. a large capacitor causes distortion on voltage sensing. 6. optimize the compensation network to improve the transient performance. the transient performance is optimized by adjusting the compensation network. for best ripple performance, select a compensation capacitor not less than 1.5nf, and select a compensation resistor not greater than 50k. 7. current limit resistor, soft-start capacitor and uvlo resistor divider use the current limit resistor r lim to lower the current limit if a compact transformer design is required. soft-start capacitor helps during the start-up of the ? yback converter . select the uvlo resistor divider for intended input opera- tion range. these equations are aforementioned. figure 9. rcd snubber in a flyback converter figure 10. typical switch node waveform 3575 f09 l s d r c v in v c nv out t sp 3575 f10 datasheet.in
LT3575 18 3575f 12v isolated flyback converter typical applications shdn /uvlo t c ss sw vc gnd bias LT3575 3575 ta02 r6 28.7k r5 10k v in 5v v out + 5v, 700ma v out C v in 3:1 d1 v in r1 200k r2 90.9k c1 10 f c5 47 f t1 24 h 2.6 h t1: pulse pa2454nl d1: pds835l d2: pmeg6010 c5: murata, grm32er71a476k r4 6.04k r3 80.6k c2 10nf c3 33nf r7 4.53k r8 1k d2 c6 0.22 f test r ilim r fb r ref shdn /uvlo t c ss sw vc gnd bias LT3575 3575 ta03 r6 59k r5 10k v in 5v v in 2:1:1 v in r1 200k r2 90.9k c1 10 f t1 33.2 h t1: coiltronics vph2-0083-r d1, d2: pds540 d3: pmeg6010 c5, c6: murata, grm32er71a476k r4 6.04k r3 118k v out1 + 12v, 200ma v out 1 C d1 c5 47 f 8.3 h v out2 + v out 2 C C12v, 200ma d2 c6 47 f 8.3 h c2 10nf c3 0.1f r7 4.99k r8 1k d3 c6 0.22 f test r ilim r fb r ref low input voltage 5v isolated flyback converter datasheet.in
LT3575 19 3575f typical applications v out + 5v, 1.4a v out C d1 c5 47 f 2.6 h t1: pulse pa2454nl or wrth elektronik 750310471/750311675 d1: pds835l d3: pmeg6010 c5: murata, grm32er71a476k shdn /uvlo t c ss sw vc gnd bias LT3575 3575 ta04 r6 28.7k r5 10k v in 12v to 24v (*30v) v in 3:1:1 r1 499k r2 71.5k c1 10 f t1 24 h r4 6.04k r3 80.6k c3 4700pf c4 4.7f c2 10nf r7 11.5k *optional third winding for 30v operation d2 l1c 2.6 h d3 test r ilim r fb r ref c6 0.22 f r8 1k 5v isolated flyback converter ef? ciency i out (a) 0 efficiency (%) 0.4 0.8 0.2 0.6 1.0 1.2 1.4 1.6 1.8 2.0 3575 ta04b 60 70 80 50 40 10 0 30 90 20 v in = 12v v in = 24v datasheet.in
LT3575 20 3575f shdn /uvlo t c ss sw vc gnd bias LT3575 3575 ta05 r6 19.1k r5 10k v in 12v to 24v (*36v) v in 4:1:1 r1 499k r2 71.5k c1 10 f t1 24 h t1: pulse pa2362nl or wrth elektronik 750310559 d1: pds835l d3: pmeg6010 r4 6.04k r3 76.8k v out + 3.3v, 1.5a v out C d1 c5 47 f 1.5 h c3 15nf c4 4.7f c2 10nf r7 4.99k *optional third winding for 36v operation d2 l1c 1.5 h test r ilim r fb r ref d3 c6 0.22 f r8 1k 3.3v isolated flyback converter typical applications datasheet.in
LT3575 21 3575f 12v isolated flyback converter shdn /uvlo t c ss sw vc gnd bias LT3575 3575 ta06 r6 59k r5 10k v in 12v v out 12v, 700ma v out C v in 3:1 d1 v in r1 499k r2 71.5k c1 10 f c5 47 f t1 40.5 h 4.5 h t1: coiltronics vp3-0055-r d1: pds835l d2: pmeg6010 r4 6.04k r3 178k c2 10nf c3 22nf r7 7.87k test r ilim r fb r ref d2 c6 0.22 f r8 1k typical applications datasheet.in
LT3575 22 3575f typical applications four output 12v isolated flyback converter shdn /uvlo t c ss sw vc gnd bias LT3575 3575 ta07 r6 59k r5 10k v in 12v to 24v v in 2:1:1:1:1 v in r1 499k r2 71.5k c1 10 f t1 33.2 h t1: coiltronics vph2-0083-r d1-d4: pds540 d5: pmeg6010 r4 6.04k r3 118k v out1 + 12v, 120ma v out 1 C d1 c5 47 f 8.3 h v out2 + 12v, 120ma v out 2 C d2 c6 47 f 8.3 h v out3 + 12v, 120ma v out 3 C d3 c7 47 f 8.3 h v out4 + 12v, 120ma v out 4 C d4 c8 47 f 8.3 h c2 10nf c3 0.1f r7 10k test r ilim r fb r ref d5 c6 0.22 f r8 1k datasheet.in
LT3575 23 3575f package description fe16 (ba) tssop 0204 0.09 C 0.20 (.0035 C .0079) 0 C 8 0.25 ref 0.50 C 0.75 (.020 C .030) 4.30 C 4.50* (.169 C .177) 134 5 6 7 8 10 9 4.90 C 5.10* (.193 C .201) 16 1514 13 12 11 1.10 (.0433) max 0.05 C 0.15 (.002 C .006) 0.65 (.0256) bsc 2.74 (.108) 2.74 (.108) 0.195 C 0.30 (.0077 C .0118) typ 2 millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in recommended solder pad layout 3. drawing not to scale 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 2.74 (.108) 2.74 (.108) see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 16-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation ba information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. datasheet.in
LT3575 24 3575f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2010 lt 0710 ? printed in usa related parts typical application 13v to 30v in , +5v/ C 5v out isolated flyback converter shdn /uvlo t c ss sw vc gnd bias LT3575 3575 ta11 r5 28.7k r6 10k v in 13v to 30v v in t1 3:1:1:1 r1 499k r2 64.9k c1 10 f l1a 63 h r4 6.04k r3 80.6k v out + +5v, 500ma com v out C C 5v, 500ma d1 c5 47 f d2 c6 47 f l1b 7 h l1c 7 h c3 15nf r7 7.68k c4 4.7f c2 10nf *optional third winding for >24v operation t1: wrth elektronik 750310564 d4: pmeg6010 d1, d2: pds835l d3 l1d 7 h test r ilim r fb r ref d4 c6 0.22 f r8 1k part number description comments lt3574/lt3573 40v isolated flyback converters monolithic no-opto flybacks with integrated 0.65a / 1.25a 60v switch lt3957/lt3958 40v/100v flyback, boost converters monolithic with integrated 5a/3.3a switch lt3757/lt3758 40v/100v flyback, boost controllers universal controllers with small package and powerful gate drive lt1737/lt1725 20v isolated flyback controller no opto-isolator or third winding required lt3825/lt3837 isolated synchronous flyback controllers no opto-isolator or third winding required lt c ? 3803/ltc3803-3 ltc3803-5 200khz/300khz flyback dc/dc controllers v in and v out limited only by external components ltc3805/ltc3805-5 adjustable frequency flyback controllers v in and v out limited only by external components datasheet.in

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